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prerelease ltm4600 1 4600p electrical specifications subject to change load current (a) 0 efficiency (%) 50 60 70 6 10 4600 ta01b 40 30 20 24 8 80 90 100 12 0.6v out 1.2v out 1.5v out 2.5v out 3.3v out 10a high ef ciency dc/dc ?odule the ltm ? 4600 is a complete 10a, dc/dc step down power supply. included in the package are the switching control- ler, power fets, inductor, and all support components. operating over an input voltage range of 4.5v to 20v, the ltm4600 supports an output voltage range of 0.6v to 5v, set by a single resistor. this high ef? ciency design delivers 10a continuous current (14a peak), needing no heat sinks or air? ow to meet power speci? cations. only bulk input and output capacitors are needed to ? nish the design. the low pro? le package (2.8mm) enables utilization of unused space on the bottom of pc boards for high density point of load regulation. high switching frequency and an adaptive on-time current mode architecture enables a very fast transient response to line and load changes without sacri? cing stability. fault protection features include integrated overvoltage and short circuit protection with a defeatable shutdown timer. a built-in soft-start timer is adjustable with a small capacitor. the ltm4600 is packaged in a thermally enhanced, compact (15mm 15mm) and low pro? le (2.8mm) over-molded land grid array (lga) package suitable for automated assembly by standard surface mount equipment. the ltm4600 is pb-free and rohs certi? ed. telecom and networking equipment servers industrial equipment point of load regulation other general purpose step down dc/dc complete switch mode power supply wide input voltage range: 4.5v to 20v 10a dc, 14a peak output current parallel two modules? for 20a output current 0.6v to 5v output voltage 1.5% regulation ultrafast transient response current mode control pb-free (e 4 ) rohs compliant package up to 92% ef? ciency programmable soft-start output overvoltage protection optional short-circuit shutdown timer small footprint, low pro? le (15mm 15mm 2.8mm) surface mount lga package 10a module power supply with 4.5v to 20v input applicatio s u features descriptio u typical applicatio u , ltc, lt and ltm are registered trademarks of linear technology corporation. module is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 5481178, 6100678, 6580258, 5847554, 6304066. ef? ciency vs load current with 12v in (fcb = 0) v in c in 4600 ta01a ltm4600 pgnd sgnd v out v oset v in 4.5v to 20v v out 1.5v 10a c out 66.5k
prerelease ltm4600 2 4600p run/ss fcb pgood v in pgnd v out comp sgnd extv cc v oset f adj sv in lga package 104-lead (15mm 15mm 2.8mm) top view fcb, extv cc , pgood, run/ss, v out .......... C0.3v to 6v v in , sv in , f adj ........................................... C0.3v to 20v v oset , comp ............................................. C0.3v to 2.7v operating temperature range (note 2) ... C40c to 85c junction temperature ........................................... 125c storage temperature range ................... C65c to 150c order part number lga part marking t jmax = 125c, ja = 15c/w consult ltc marketing for parts speci? ed with wider operating temperature ranges. ltm4600ev LTM4600IV ltm4600ev LTM4600IV (note 1) the denotes the speci? cations which apply over the C40c to 85c temperature range, otherwise speci? cations are at t a = 25c, v in = 12v. external c in = 120f, c out = 200f/ceramic per typical application (front page) con? guration. electrical characteristics absolute axi u rati gs w ww u package/order i for atio uu w symbol parameter conditions min typ max units v in(dc) input dc voltage 4.5 20 v v out(dc) output voltage v in = 12v, v out = 1.5v, i out = 0a v in = 12v, v out = 1.5v, i out = 0a v in = 5v, v out = 1.5v, i out = 0a fcb = 0 1.478 1.50 1.522 v input speci? cations v in(uvlo) under voltage lockout threshold i out = 0a 3.4 4 v i inrush(vin) input inrush current at startup v in = 5v v in = 12v i out = 0a. v out = 1.5v, fcb = 0 0.6 0.7 a a i q(vin) input supply bias current v in = 12v, v out = 1.5v, fcb = 5v v in = 12v, v out = 1.5v, fcb = 0v v in = 5v, v out = 1.5v, fcb = 5v v in = 5v, v out = 1.5v, fcb = 0v shutdown, run = 0, v in = 12v i out = 0a, extv cc open 1.2 42 1.0 52 15 ma ma ma ma a i s(vin) input supply current v in = 12v, v out = 1.5v, i out = 10a v in = 12v, v out = 3.3v, i out = 10a v in = 5v, v out = 1.5v, i out = 10a 1.52 3.13 3.64 a a a
prerelease ltm4600 3 4600p note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: the ltm4600e is guaranteed to meet performance speci? cations from 0c to 85c. speci? cations over the C40c to 85c operating temperature range are assured by design, characterization and correlation with statistical process controls. the ltm4600i is guaranteed and tested over the C40c to 85c temperature range. symbol parameter conditions min typ max units output speci? cations i outdc output continuous current range (see output current derating curves for different v in , v out and t a ) v in = 12v, v out = 1.5v 0 10 a v out / v in line regulation accuracy i out = 0a v out = 1.5v. fcb = 0v 0.3 % v out / i out load regulation accuracy v in = 5v v in = 12v v out = 1.5v. fcb = 0v 0a to 10a 1 1 % % v out(ac) output ripple voltage v in = 12v, v out = 1.5v, fcb = 0v v in = 5v, v out = 1.5v, fcb = 0v i out = 0a 15 20 25 mv p-p mv p-p fs output ripple voltage frequency fcb = 0v, i out = 5a, v in = 12v, v out = 1.5v 800 khz t start turn-on time v in = 12v v in = 5v v out = 1.5v, i out = 10a 0.5 0.7 ms ms v outls voltage drop for dynamic load step v in = 12v, v out = 1.5v load step: 0a to 5a/s c out = 3 ? 22f 6.3v, 470f 4v pos cap, see table 2 36 mv t settle settling time for dynamic load step v in = 12v load: 10% to 90% to 10% of full load 25 s i outpk output current limit v in = 12v, v out = 1.5v v in = 5v, v out = 1.5v 17 17 a a control stage v oset voltage at v oset pin i out = 0a, v out = 1.5v 0.594 0.6 0.606 v v run/ss run on/off threshold 0.8 1.5 2 v i run(c)/ss soft-start charging current v run/ss = 0v C0.5 C1.2 C3 a i run(d)/ss soft-start discharging current v run/ss = 4v 0.8 1.8 3 a v in C sv in extv cc = 0, fcb = 0v 100 mv i extvcc current into extv cc pin fcb = 0v, v out = 1.5v, i out = 0a 16 ma r fbhi resistor between v out and fb pins 100 k v fcb forced continuous threshold 0.57 0.6 0.63 v i fcb forced continuous pin current v fcb = 0.6v C1 C2 a pgood output v oseth pgood upper threshold v oset rising 7.5 10 12.5 % v osetl pgood lower threshold v oset falling C7.5 C10 C12.5 % v oset(hys) pgood hysteresis v oset returning 1 2.5 % v pgl pgood low voltage i pgood = 5ma 0.15 0.4 v the denotes the speci? cations which apply over the C40c to 85c temperature range, otherwise speci? cations are at t a = 25c, v in = 12v. per typical application (front page) con? guration. electrical characteristics
prerelease ltm4600 4 4600p load current (a) 0 efficiency (%) 50 60 70 6 10 4600 g02 40 30 20 24 8 80 90 100 12 0.6v out 1.2v out 1.5v out 2.5v out 3.3v out ef? ciency vs load current w ith 5v in (fcb = 0) typical perfor a ce characteristics uw load current (a) 0 100 90 80 70 60 50 40 30 610 4600 g01 24 812 efficiency (%) 0.6v out 1.2v out 1.5v out 2.5v out ef? ciency vs load current with 12v in ( fcb = 0 ) ef? ciency vs load current with 18v in (fcb = 0) load current (a) 0 efficiency (%) 6 10 4600 g03 24 8 12 80 90 100 70 60 50 40 30 1.5v out 1.8v out 2.5v out 3.3v out ef? ciency vs load current with different fcb settin g s load current (a) 20 50 40 30 90 80 70 60 4600 g04 efficiency (%) 0.1 10 1 fcb = gnd fcb > 0.7v 1.2v transient response (see figure 17) 1.5v transient response (see figure 17) 1.8v transient response ( see fi g ure 17 ) 2.5v transient response ( see fi g ure 17 ) 3.3v transient response ( see fi g ure 17 ) 25s/div 4600 g05 1.2v at 5a/s load step c out = 3 ? 22f 6.3v ceramics 470f 4v sanyo pos cap c3 = 100pf 25s/div 4600 g06 1.5v at 5a/s load step c out = 3 ? 22f 6.3v ceramics 470f 4v sanyo pos cap c3 = 100pf 25s/div 4600 g07 1.8v at 5a/s load step c out = 3 ? 22f 6.3v ceramics 470f 4v sanyo pos cap c3 = 100pf 25s/div 4600 g08 2.5v at 5a/s load step c out = 3 ? 22f 6.3v ceramics 470f 4v sanyo pos cap c3 = 100pf 25s/div 4600 g09 3.3v at 5a/s load step c out = 3 ? 22f 6.3v ceramics 470f 4v sanyo pos cap c3 = 100pf v out = 50mv/div i out = 5a/div
prerelease ltm4600 5 4600p v in (v) 0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 515 4600 g17 10 20 v out (v) 5v 3.3v 2.5v 1.8v 1.5v 1.2v 0.6v output voltage (v) 0 18 16 14 12 10 8 6 4 2 0 4600 g16 4.0 3.5 3.0 2.5 2.0 1.0 0.5 1.5 output current (a) output voltage (v) 0 18 16 14 12 10 8 6 4 2 0 4600 g14 6 5 4 3 2 1 current limit (a) typical perfor a ce characteristics uw start-up, i out = 0a (see figure 17) start-up, i out = 10a ( resistive load ) ( see fi g ure 17 ) short-circuit protection, i out = 0a ( see fi g ure 17 ) short-circuit protection, i out = 10a ( see fi g ure 17 ) 200s/div 4600 g10 v in = 12v v out = 1.5v c out = 200f no external soft-start capacitor v out (0.5v/div) i in (0.5a/div) 200s/div 4600 g11 v in = 12v v out = 1.5v c out = 200f no external soft-start capacitor v out (0.5v/div) i in (0.5a/div) 20s/div 4600 g12 v in = 12v v out = 1.5v c out = 2 200f/x5r no external soft-start capacitor v out (0.5v/div) i in (0.2a/div) 20s/div 4600 g13 v in = 12v v out = 1.5v c out = 2 200f/x5r no external soft-start capacitor v out (0.5v/div) i in (0.5a/div) current limit with 12v in current limit with 9v in current limit with 5v in output voltage (v) 0 18 16 14 12 10 8 6 4 2 0 4600 g15 6 5 4 3 2 1 current limit (a) v in to v out stepdown ratio
prerelease ltm4600 6 4600p pi fu ctio s uuu v in (bank 1): power input pins. apply input voltage between these pins and gnd pins. recommend placing input decoupling capacitance directly between v in pins and gnd pins. f adj (pin a15): an internal resistor from v in to this pin sets the one-shot timer current, thereby setting the switch- ing frequency. sv in (pin a17): supply pin for internal pwm controller. leave this pin open or add additional decoupling capaci- tance. extv cc (pin a19): external 5v supply pin for controller. if left open, the internal 5v linear regulator will power the controller and mosfet drivers. for high input voltage applications, connecting this pin to an external 5v will reduce the power loss in the power module. the extv cc voltage should never be higher than v in . v oset (pin a21): the negative input of the error am- pli? er. internally, this pin is connected to v out with a 100k precision resistor. different output voltages can be programmed with additional resistors between the v oset and sgnd pins. comp (pin b23): current control threshold and error ampli? er compensation point. the current comparator threshold increases with this control voltage. the voltage ranges from 0v to 2.4v with 0.8v corresponding to zero sense voltage (zero current). sgnd (pin d23): signal ground pin. all small-signal components should connect to this ground, which in turn connects to pgnd at one point. run/ss (pin f23): run and soft-start control. forcing this pin below 0.8v will shut down the power supply. inside the power module, there is a 1000pf capacitor which provides approximately 0.7ms soft-start time with 200f output capacitance. additional soft-start time can be achieved by adding additional capacitance between the run/ss and sgnd pins. the internal short-circuit latchoff can be disabled by adding a resistor between this pin and the v in pin. this resistor must supply a minimum 5a pull up current. fcb (pin g23): forced continuous input. grounding this pin enables forced continuous mode operation regardless of load conditions. tying this pin above 0.63v enables discontinuous conduction mode to achieve high ef? ciency operation at light loads. there is an internal 4.75k resistor between the fcb and sgnd pins. pgood (pin j23): output voltage power good indicator. when the output voltage is within 10% of the nominal voltage, the pwrgd is open drain output. otherwise, this pin is pulled to ground. pgnd (bank 2): power ground pins for both input and output returns. v out (bank 3): power output pins. apply output load between these pins and gnd pins. recommend placing high frequency output decoupling capacitance directly between these pins and gnd pins. (see package description for pin assignment) e c a run/ss fcb pgood v in bank 1 pgnd bank 2 v out bank 3 comp sgnd extv cc v oset f adj sv in top view 35 24 79 68 11 13 10 12 15 17 14 16 19 21 18 20 22 94 95 96 97 98 99 100 101 102 103 104 93 82 71 60 49 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 40 51 62 73 84 85 86 87 88 89 90 91 74 75 76 77 78 79 80 63 64 65 66 67 68 69 52 53 54 55 56 57 58 42 43 44 45 46 47 92 81 70 59 48 11 10 9 13 14 15 26 27 28 29 30 31 33 34 35 36 37 38 41 1 8 12 25 32 39 50 61 72 83 1 23 b d f g h j l m n p r s k 4600 pn01
prerelease ltm4600 7 4600p w u decoupli g require e ts u symbol parameter conditions min typ max units c in external input capacitor requirement (v in = 4.5v to 15v, v out = 1.5v) i out = 10a 20 f c out external output capacitor requirement (v in = 4.5v to 15v, v out = 1.5v) i out = 10a, refer to table 2 in the applications information section 100 200 f si plified w block diagra w t a = 25c, v in = 12v. use figure 1 con? guration. figure 1. simpli? ed ltm4600 block diagram 4600 f01 run/ss ltm4600 v oset extv cc sgnd f adj fcb 1000pf q1 q2 v out 1.5v/10a max pgnd v in 4.5v to 20v sv in comp pgood r6 66.5k 100k 0.5% 4.75k 1.5 f c in 15 f 6.3v c out 10 ? int comp controller
prerelease ltm4600 8 4600p operatio u module description the ltm4600 is a standalone non-isolated synchronous switching dc/dc power supply. it can deliver up to 10a of dc output current with only bulk external input and output capacitors. this module provides a precisely regulated output voltage programmable via one external resistor from 0.6v dc to 5.0v dc , not to exceed 80% of the input voltage. the input voltage range is 4.5v to 20v. a simpli? ed block diagram is shown in figure 1 and the typical application schematic is shown in figure 17. the ltm4600 contains an integrated ltc constant on-time current-mode regulator, ultra-low r ds(on) fets with fast switching speed and integrated schottky diode. the typical switching frequency is 800khz at full load. with current mode control and internal feedback loop compensation, the ltm4600 module has suf? cient stability margins and good transient performance under a wide range of operat- ing conditions and with a wide range of output capacitors, even all ceramic output capacitors. current mode control provides cycle-by-cycle fast current limit. in addition, foldback current limiting is provided in an over-current condition while v fb drops. also, the ltm4600 has defeatable short circuit latch off. internal overvolt- age and undervoltage comparators pull the open-drain pgood output low if the output feedback voltage exits a 10% window around the regulation point. furthermore, in an overvoltage condition, internal top fet q1 is turned off and bottom fet q2 is turned on and held on until the overvoltage condition clears. pulling the run/ss pin low forces the controller into its shutdown state, turning off both q1 and q2. releasing the pin allows an internal 1.2a current source to charge up the softstart capacitor. when this voltage reaches 1.5v, the controller turns on and begins switching. at low load current the module works in continuous cur- rent mode by default to achieve minimum output voltage ripple. it can be programmed to operate in discontinuous current mode for improved light load ef? ciency when the fcb pin is pulled up above 0.8v and no higher than 5v. the fcb pin has a 4.25k resistor to ground, so a resistor to v in can set the voltage on the fcb pin. when extv cc pin is grounded, an integrated 5v linear regulator powers the controller and mosfet gate drivers. if a minimum 4.7v external bias supply is applied on the extv cc pin, the internal regulator is turned off, and an internal switch connects extv cc to the gate driver voltage. this eliminates the linear regulator power loss with high input voltage, reducing the thermal stress on the controller. the maximum voltage on extv cc pin is 6v. the extv cc voltage should never be higher than the v in voltage. also extv cc must be sequenced after v in .
prerelease ltm4600 9 4600p applicatio s i for atio wu u u down when q down is on and q up is off. if the output voltage v o needs to be margined up/down by m%, the resistor values of r up and r down can be calculated from the following equations: ()(%) () . rr v m rr k v set up o set up 1 100 06 + +? = rv m rkr v set o set down (?%) () . 1 100 06 +? = input capacitors the ltm4600 module should be connected to a low ac-impedance ac source. high frequency, low esr input capacitors are required to be placed adjacent to the mod- ule. in figure 20, the bulk input capacitor c in is selected for its ability to handle the large rms current into the converter. for a buck converter, the switching duty-cycle can be estimated as: d v v o in = without considering the inductor current ripple, the rms current of the input capacitor can be estimated as: i i dd cin rms omax () () % ( ) =? 1 in the above equation, % is the estimated ef? ciency of the power module. c1 can be a switcher-rated electrolytic aluminum capacitor, os-con capacitor or high volume ceramic capacitors. note the capacitor ripple current ratings are often based on only 2000 hours of life. this makes it advisable to properly derate the input capacitor, or choose a capacitor rated at a higher temperature than required. always contact the capacitor manufacturer for derating requirements. in figure 16, the input capacitors are used as high fre- quency input decoupling capacitors. in a typical 10a output application, 1-2 pieces of very low esr x5r or x7r, 10f ceramic capacitors are recommended. this decoupling capacitor should be placed directly adjacent the typical ltm4600 application circuit is shown in figure 20. external component selection is primarily determined by the maximum load current and output voltage. output voltage programming and margining the pwm controller of the ltm4600 has an internal 0.6v1% reference voltage. as shown in the block diagram, a 100k/0.5% internal feedback resistor connects v out and fb pins. adding a resistor r set from v oset pin to sgnd pin programs the output voltage: vv kr r o set set = + 06 100 . table 1 shows the standard vaules of 1% r set resistor for typical output voltages: table 1. r set (k ) open 100 66.5 49.9 43.2 31.6 22.1 13.7 v o (v) 0.6 1.2 1.5 1.8 2 2.5 3.3 5 voltage margining is the dynamic adjustment of the output voltage to its worst case operating range in production testing to stress the load circuitry, verify control/protec- tion functionality of the board and improve the system reliability. figure 2 shows how to implement margining function with the ltm4600. in addition to the feedback resistor r set , several external components are added. turn off both transistor q up and q down to disable the margining. when q up is on and q down is off, the output voltage is margined up. the output voltage is margined figure 2. pgnd sgnd 4600 f02 ltm4600 v out v oset r set r up q up 100k 2n7002 r down q down 2n7002
prerelease ltm4600 10 4600p applicatio s i for atio wu u u the module input pins in the pcb layout to minimize the trace inductance and high frequency ac noise. output capacitors the ltm4600 is designed for low output voltage ripple. the bulk output capacitors c out is chosen with low enough effective series resistance (esr) to meet the output voltage ripple and transient requirements. c out can be low esr tantalum capacitor, low esr polymer capacitor or ceramic capacitor. the typical capacitance is 200f if all ceramic output capacitors are used. the internally optimized loop compensation provides suf? cient stability margin for all ceramic capacitors applications. additional output ? lter- ing may be required by the system designer, if further reduction of output ripple or dynamic transient spike is required. refer to table 2 for an output capacitance matrix for each output voltage droop, peak to peak deviation and recovery time during a 5a/s transient with a speci? c output capacitance. fault conditions: current limit and over current foldback the ltm4600 has a current mode controller, which inher- ently limits the cycle-by-cycle inductor current not only in steady state operation, but also in transient. to further limit current in the event of an over load condi- tion, the ltm4600 provides foldback current limiting. if the output voltage falls by more than 50%, then the maximum output current is progressively lowered to about one sixth of its full current limit value. soft-start and latchoff with the run/ss pin the run/ss pin provides a means to shut down the ltm4600 as well as a timer for soft-start and over-cur- rent latchoff. pulling the run/ss pin below 0.8v puts the ltm4600 into a low quiescent current shutdown (i q 30a). releasing the pin allows an internal 1.2a cur- rent source to charge up the timing capacitor css. inside ltm4600, there is an internal 1000pf capacitor from run/ss pin to ground. if run/ss pin has an external capacitor css_ext to ground, the delay before starting is about: t v a cpf delay ss ext = + 15 12 1000 . . ( ) _ when the voltage on run/ss pin reaches 1.5v, the ltm4600 internal switches are operating with a clamping of the maximum output inductor current limited by the run/ss pin total soft-start capacitance. as the run/ss pin voltage rises to 3v, the soft-start clamping of the inductor current is released. v in to v out stepdown ratios there are restrictions in the maximum v in to v out step down ratio that can be achieved for a given input voltage. these contraints are shown in the typical performance characteristics curves labeled v in to v out stepdown ratio. note that additional thermal de-rating may apply. see the thermal considerations and output current de- rating sections of this data sheet.
prerelease ltm4600 11 4600p applicatio s i for atio wu u u table 2. output voltage response verses component matrix typical measured values c out1 vendors part number c out2 vendors part number tdk c4532x5r0j107mz (100uf,6.3v) sanyo pos cap 6tpe330mil (330f, 6.3v) taiyo yuden jmk432bj107mu-t ( 100f, 6.3v) sanyo pos cap 2r5tpe470m9 (470f, 2.5v) taiyo yuden jmk316bj226ml-t501 ( 22f, 6.3v) sanyo pos cap 4tpe470mcl (470f, 4v) v out (v) c in (ceramic) c in (bulk) c out1 (ceramic) c out2 (bulk) c comp c3 v in (v) droop (mv) peak to peak (mv) recovery time (s) load step (a/s) 1.2 2 10f 25v 150f 35v 3 22f 6.3v 470f 4v none 100pf 12 35 68 25 5 1.2 2 10f 25v 150f 35v 3 22f 6.3v 470f 4v none 100pf 5 35 68 25 5 1.5 2 10f 25v 150f 35v 3 22f 6.3v 470f 4v none 100pf 12 36 75 25 5 1.5 2 10f 25v 150f 35v 3 22f 6.3v 470f 4v none 100pf 5 36 75 25 5 1.8 2 10f 25v 150f 35v 3 22f 6.3v 470f 4v none 100pf 12 40 81 30 5 1.8 2 10f 25v 150f 35v 3 22f 6.3v 470f 4v none 100pf 5 40 81 30 5 2.5 2 10f 25v 150f 35v 3 22f 6.3v 470f 4v none 100pf 12 51 102 30 5 2.5 2 10f 25v 150f 35v 3 22f 6.3v 470f 4v none 100pf 5 57 116 30 5 3.3 2 10f 25v 150f 35v 3 22f 6.3v 470f 4v none 100pf 12 64 129 35 5 3.3 2 10f 25v 150f 35v 3 22f 6.3v 470f 4v none 100pf 7 82 166 35 5 1.2 2 10f 25v 150f 35v 1 100f 6.3v 470f 2.5v none 100pf 12 35 70 20 5 1.2 2 10f 25v 150f 35v 1 100f 6.3v 470f 2.5v none 100pf 5 35 70 20 5 1.5 2 10f 25v 150f 35v 1 100f 6.3v 470f 2.5v none 100pf 12 37 79 20 5 1.5 2 10f 25v 150f 35v 1 100f 6.3v 470f 2.5v none 100pf 5 37 79 20 5 1.8 2 10f 25v 150f 35v 1 100f 6.3v 470f 2.5v none 100pf 12 44 85 20 5 1.8 2 10f 25v 150f 35v 1 100f 6.3v 470f 2.5v none 100pf 5 44 88 20 5 2.5 2 10f 25v 150f 35v 1 100f 6.3v 470f 4v none 100pf 12 48 103 30 5 2.5 2 10f 25v 150f 35v 1 100f 6.3v 470f 4v none 100pf 5 48 103 30 5 3.3 2 10f 25v 150f 35v 1 100f 6.3v 470f 4v none 100pf 12 52 106 30 5 3.3 2 10f 25v 150f 35v 1 100f 6.3v 470f 4v none 100pf 7 66 132 30 5 1.2 2 10f 25v 150f 35v 2 100f 6.3v 330f 6.3v none 100pf 12 40 80 20 5 1.2 2 10f 25v 150f 35v 2 100f 6.3v 330f 6.3v none 100pf 5 40 80 20 5 1.5 2 10f 25v 150f 35v 2 100f 6.3v 330f 6.3v none 100pf 12 44 89 20 5 1.5 2 10f 25v 150f 35v 2 100f 6.3v 330f 6.3v none 100pf 5 44 84 20 5 1.8 2 10f 25v 150f 35v 2 100f 6.3v 330f 6.3v none 100pf 12 44 91 20 5 1.8 2 10f 25v 150f 35v 2 100f 6.3v 330f 6.3v none 100pf 5 46 91 20 5 2.5 2 10f 25v 150f 35v 2 100f 6.3v 330f 6.3v none 100pf 12 56 113 30 5 2.5 2 10f 25v 150f 35v 2 100f 6.3v 330f 6.3v none 100pf 5 56 113 30 5 3.3 2 10f 25v 150f 35v 2 100f 6.3v 330f 6.3v none 100pf 12 64 126 30 5 3.3 2 10f 25v 150f 35v 2 100f 6.3v 330f 6.3v none 100pf 7 64 126 30 5 1.2 2 10f 25v 150f 35v 4 100f 6.3v none none 100pf 12 49 98 20 5 1.2 2 10f 25v 150f 35v 4 100f 6.3v none none 100pf 5 49 98 20 5 1.5 2 10f 25v 150f 35v 4 100f 6.3v none none 100pf 12 54 108 20 5 1.5 2 10f 25v 150f 35v 4 100f 6.3v none none 100pf 5 61 118 20 5 1.8 2 10f 25v 150f 35v 4 100f 6.3v none none 100pf 12 62 125 20 5 1.8 2 10f 25v 150f 35v 4 100f 6.3v none none 100pf 5 62 128 20 5 2.5 2 10f 25v 150f 35v 4 100f 6.3v none none 100pf 12 70 159 25 5 2.5 2 10f 25v 150f 35v 4 100f 6.3v none none 100pf 5 60 115 25 5 3.3 2 10f 25v 150f 35v 4 100f 6.3v none none 100pf 12 76 144 25 5 3.3 2 10f 25v 150f 35v 4 100f 6.3v none none 100pf 7 100 200 25 5 52 10f 25v 150f 35v 4 100f 6.3v none none 100pf 15 188 375 25 5 52 10f 25v 150f 35v 4 100f 6.3v none none 100pf 20 159 320 25 5
prerelease ltm4600 12 4600p applicatio s i for atio wu u u after the controller has been started and given adequate time to charge up the output capacitor, css is used as a short-circuit timer. after the run/ss pin charges above 4v, if the output voltage falls below 75% of its regulated value, then a short-circuit fault is assumed. a 1.8a current then begins discharging css. if the fault condition persists until the run/ss pin drops to 3.5v, then the controller turns off both power mosfets, shuting down the converter permanently. the run/ss pin must be actively pulled down to ground in order to restart operation. the over-current protection timer requires the soft-start timing capacitor css be made large enough to guarantee that the output is in regulation by the time css has reached the 4v threshold. in general, this will depends upon the size of the output capacitance, output voltage and load current characteristic. a minimum external soft-start capacitor can be estimated from: cpfcvfv ss ext out out s _ ? ([/]) +> 1000 10 3 generally 0.1f is more than suf? cient. since the load current is already limited by the current mode control and current foldback circuitry during a shortcircuit, over-current latchoff operation is not always needed or desired, especially the output has large amount of capacitance or the load draw huge current during start up. the latchoff feature can be overridden by a pull-up current greater than 5a but less than 80a to the run/ss pin. the additional current prevents the discharge of css during a fault and also shortens the soft-start period. us- ing a resistor from run/ss pin to v in is a simple solution v in v in 500k run/ss 4600 f04 ltm4600 pgnd sgnd figure 4. defeat short-circuit latchoff with a pull-up resistor to v in figure 3. run/ss pin voltage during startup and short-circuit protection v run/ss 3.5v t t 75%v o switching starts soft-start clamping of i l released short-circuit latchoff output overload happens short-circuit latch armed 4v 3v 1.5v 4600 f03 v o to defeat latchoff. any pull-up network must be able to maintain run/ss above 4v maximum latchoff threshold and overcome the 4a maximum discharge current. figure 3 shows a conceptual drawing of v run during startup and short circuit.
prerelease ltm4600 13 4600p enable the run/ss pin can be driven from logic as shown in figure 5. this function allows the ltm4600 to be turned on or off remotely. the on signal can also control the sequence of the output voltage. figure 5. enable circuit with external logic run/ss 4600 f05 ltm4600 pgnd 2n7002 sgnd on figure 6. output voltage tracking with the ltc2923 controller q1 v cc v in v in r onb v in 5v r tb1 r tb2 49.9k 1.8v 3.3v r ta2 r ta1 r ona on rampbuf track1 track2 fb1 gate ltc2923 gnd 4600 f06 ramp 66.5k 1.5v ltm4600 v in v out ltm4600 dc/dc v in v out v oset v oset fb2 sdo status output voltage tracking for the applications that require output voltage tracking, several ltm4600 modules can be programmed by the power supply tracking controller such as the ltc2923. figure 6 shows a typical schematic with ltc2923. coin- applicatio s i for atio wu u u cident, ratiometric and offset tracking for v o rising and falling can be implemented with different sets of resistor values. see the ltc2923 data sheet for more details. extv cc connection an internal low dropout regulator produces an internal 5v supply that powers the control circuitry and fet drivers. therefore, if the system does not have a 5v power rail, the ltm4600 can be directly powered by v in . the gate driver current through ldo is about 18ma. the internal ldo power dissipation can be calculated as: p ldo_loss = 18ma ? (v in C 5v) the ltm4600 also provides an external gate driver volt- age pin extv cc . if there is a 5v rail in the system, it is recommended to connect extv cc pin to the external 5v rail. whenever the extv cc pin is above 4.7v, the internal 5v ldo is shut off and an internal 50ma p-channel switch connects the extv cc to internal 5v. internal 5v is supplied from extv cc until this pin drops below 4.5v. do not apply more than 6v to the extv cc pin and ensure that extv cc < v in . the following list summaries the possible connec- tions for extv cc : 1. extv cc grounded. internal 5v ldo is always powered from the internal 5v regulator. 2. extv cc connected to an external supply. internal ldo is shut off. a high ef? ciency supply compatible with the mosfet gate drive requirements (typically 5v) can im- prove overall ef? ciency. with this connection, it is always required that the extv cc voltage can not be higher than v in pin voltage. discontinuous operation and fcb pin the fcb pin determines whether the internal bottom mosfet remains on when the inductor current reverses. there is an internal 4.75k pulling down resistor connecting this pin to ground. the default light load operation mode is forced continuous (pwm) current mode. this mode provides minimum output voltage ripple.
prerelease ltm4600 14 4600p applicatio s i for atio wu u u thermal considerations and output current derating the power loss curves in figures 8 and 13 can be used in coordination with the load current de-rating curves in figures 9 to 12 and figures 14 to 15 for calculating an approximate ja for the module. each of the load current de-rating curves will lower the maximum load current as a function of the increased ambient temperature to keep the maximum junction temperature of the power module at 100c maximum. this 100c maximum is to allow for an increased rise of about 15c to 20c inside the module. this will maintain the maximum operating temperature to below 125c. each of the de-rating curves and the power loss curve that corresponds to the correct output voltage can be used to solve for the approximate ja of the condition. each figure has three curves that are taken at three different air ? ow conditions. for example in figure 9, the 10a load current can be achieved up to 60c ambient temperature with no air ? ow. if this 60c is subtracted from the maximum module temperature of 100c, then 40c is the maximum temperature rise. now figure 8 records the power loss for this 5v to 1.5v at the 10a output. if we take the 40c rise and divided it by the 3 watts of loss, then we get an approximate ja of 13.5c/w with no heatsink. if we take the next air ? ow curve in figure 9 at 200lfm of air ? ow, then the maximum ambient temperature allowed at 10a load current is 65c. this calculates to a 35c rise, and an approximate ja of 11.6c/w with no heatsink. in the next air ? ow curve at 400lfm in figure 9, the maximum ambient temperature allowed at 10a load current is 73c. this calculates to a 27c rise, and an approximate ja of 9c/w with no heatsink. each of the de-rating curves in figures 9 to 12 or figures 14 to 15 can be used with the appropriate power loss curve in either ? gure 8 or ? gure 13 to derive an approximate ja . table 3 and 4 provide the approximate ja for figures 9 to 12, and figures 14 to 15. a complete explanation of the thermal characteristics is provided in the thermal application note for the ltm4600. in the application where the light load ef? ciency is im- portant, tying the fcb pin above 0.6v threshold enables discontinuous operation where the bottom mosfet turns off when inductor current reverses. therefore, the conduc- tion loss is minimized and light load ef? cient is improved. the penalty is that the controller may skip cycle and the output voltage ripple increases at light load. paralleling operation with load sharing two or more ltm4600 modules can be paralleled to provide higher than 10a output current. figure 7 shows the neces- sary interconnection between two paralleled modules. the opti-loop? current mode control ensures good current sharing among modules to balance the thermal stress. the new feedback equation for two or more ltm4600s in parallel is: vv k n r r out set set = + 06 100 . where n is the number of ltm4600s in parallel. figure 7. parallel two modules with load sharing v in v out v in v out (20a max ) 4600 f07 ltm4600 pgnd sgnd comp v oset r set v in v out ltm4600 pgnd sgnd comp v oset opti-loop is a trademark of linear technology corporation.
prerelease ltm4600 15 4600p ambient temperature ( c) 50 maximum load current (a) 70 4600 f12 60 10 9 8 7 6 5 3 4 80 90 100 v in = 12v v o = 1.5v 400 lfm 200 lfm 0 lfm figure 12. bga heatsink ambient temperature ( c) 50 55 70 4600 f11 60 65 75 80 85 90 v in = 12v v o = 1.5v 400 lfm 200 lfm 0 lfm maximum load current (a) 10 9 8 7 6 5 4 figure 11. no heatsink ambient temperature ( c) 50 maximum load current (a) 70 4600 f10 60 80 90 100 v in = 5v v o = 1.5v 400 lfm 200 lfm 0 lfm 10 9 8 7 6 5 4 figure 10. bga heatsink applicatio s i for atio wu u u ambient temperature ( c) 50 70 4600 f09 60 80 90 v in = 5v v o = 1.5v 400 lfm 200 lfm 0 lfm maximum load current (a) 10 9 8 7 6 5 4 figure 9. no heatsink output current (a) 08 6 4600 f08 24 10 3.5 4.0 4.5 3.0 2.5 2.0 1.5 1.0 0.5 0 power loss (w) 12v loss 5v loss figure 8. power loss vs load current
prerelease ltm4600 16 4600p applicatio s i for atio wu u u output current (a) 08 6 4600 f13 24 10 3.5 4.0 5.0 4.5 3.0 2.5 2.0 1.5 1.0 0.5 0 power loss (w) 12v loss figure 13. power loss vs load current ambient temperature ( c) 40 70 4600 f14 60 50 80 90 v in = 12v v o = 3.3v 400 lfm 200 lfm 0 lfm maximum load current (a) 10 9 8 7 6 4 5 0 1 2 3 figure 14. no heatsink ambient temperature ( c) 40 50 maximum load current (a) 70 4600 f15 60 80 90 100 v in = 12v v o = 3.3v 400 lfm 200 lfm 0 lfm 10 9 8 7 6 5 4 figure 15. bga heatsink
prerelease ltm4600 17 4600p applicatio s i for atio wu u u table 4. 3.3v output de-rating curve v in (v) power loss curve air flow (lfm) heatsink* ja (c/w) figure 14 12 figure 8 0 none 13.5 figure 14 12 figure 8 200 none 11.6 figure 14 12 figure 8 400 none 10.4 figure 15 12 figure 8 0 bga heatsink 9.5 figure 15 12 figure 8 200 bga heatsink 6 figure 15 12 figure 8 400 bga heatsink 4.77 table 3. 1.5v output de-rating curve v in (v) power loss curve air flow (lfm) heatsink* ja (c/w) figures 9, 11 5, 12 figure 8 0 none 13.5 figures 9, 11 5, 12 figure 8 200 none 11 figures 9, 11 5, 12 figure 8 400 none 9 figures 10, 12 5, 12 figure 8 0 bga heatsink 9.5 figures 10, 12 5, 12 figure 8 200 bga heatsink 6.25 figures 10, 12 5, 12 figure 8 400 bga heatsink 4.5 *heatsink manufacturer: wake? eld engineering #cis20069
prerelease ltm4600 18 4600p applicatio s i for atio wu u u figure 16. recommended pcb layout v in pgnd top layer v out 4600 f16 load c in safety considerations the ltm4600 modules do not provide isolation from v in to v out . there is no internal fuse. if required, a slow blow fuse with a rating twice the maximum input current should be provided to protect each unit from catastrophic failure. layout checklist/example the high integration of the ltm4600 makes the pcb board layout very simple and easy. however, to optimize its electri- cal and thermal performance, some layout considerations are still necessary. ? use large pcb copper areas for high current path, in- cluding v in , pgnd and v out . it helps to minimize the pcb conduction loss and thermal stress ? place high frequency ceramic input and output capaci- tors next to the v in , pgnd and v out pins to minimize high frequency noise ? place a dedicated power ground layer underneath the unit ? to minimize the via conduction loss and reduce module thermal stress, use multiple vias for interconnection between top layer and other power layers ? do not put via directly on pad ? use a separated sgnd ground copper area for com- ponents connected to signal pins. connect the sgnd to pgnd underneath the unit figure 16 gives a good example of the recommended layout.
prerelease ltm4600 19 4600p typical applicatio u figure 17. typical application, 5v to 20v input, 0.6v to 5v output, 10a max 4600 f20 v out extv cc f adj v oset fcb comp pgood v out (multiple pins) v out run/ss sgnd pgnd (multiple pins) c2 22 f 6.3v 3 refer to table 2 c out 470 f refer to table 2 gnd 0.6v to 5v c4 opt v in 5v to 20v gnd c in 10 f 2x c1 150 f c3 100pf r1 66.5k refer to table 2 v in (multiple pins) ltm4600 sv in +
prerelease ltm4600 20 4600p typical applicatio u 4600 f17 r4 15.8k 1% extv cc run comp fcb v out v out = 0.6v ([100k/n] + r set )/r set where n = 2 c1, c3, c7, c8: tdk c3216x5r1e106mt c2, c9: taiyo yuden, jmk316bj226ml-t501 c5, c10: sanyo pos cap, 4tpe470mcl pgood fb sv in pgnd sgnd 2.5v at 20a 4.5v to 20v 2.5v 2.5v c7 10 f 25v c8 10 f 25v c10 470 f 4v c9 22 f x3 v in ltm4600 f set r1 100k extv cc run comp fcb v out pgood fb sv in pgnd sgnd c1 10 f 25v run/soft-start c3 10 f 25v c4 220pf c5 470 f 4v c2 22 f x3 v in ltm4600 f set total load 0 individual share 12 10 8 6 4 2 0 5 10 15 20 4600 f18 25 i out1 i out2 12v in 2.5v out 20a max current sharing between two ltm4600 modules parallel operation and load sharing
prerelease ltm4600 21 4600p package descriptio u lga package 104-lead (15mm 15mm) (reference ltm dwg # 05-05-1800) notes: 1. dimensioning and tolerancing per asme y14.5m-1994 2. all dimensions are in millimeters land designation per jesd mo-222, spp-010 5. primary datum -z- is seating plane 6. the total number of pads: 104 4 3 details of pad #1 identifier are optional, but must be located within the zone indicated. the pad #1 identifier is a marked feature or a notched beveled pad symbol aaa bbb eee tolerance 0.15 0.10 0.15 2.72 ? 2.92 detail b detail b substrate mold cap 0.27 ? 0.37 2.45 ? 2.55 bbb z z 15 bsc top view 15 bsc 4 pad 1 corner x y aaa z aaa z 13.97 bsc 12.70 bsc 0.11 ? 0.27 13.93 bsc 35 24 79 68 11 13 10 12 15 17 14 16 19 21 18 20 22 4600 02-18 bottom view c(0.30) pad 1 3 pads see notes 94 95 96 97 98 99 100 101 102 103 104 93 82 71 60 49 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 40 51 62 73 84 85 86 87 88 89 90 91 74 75 76 77 78 79 80 63 64 65 66 67 68 69 52 53 54 55 56 57 58 42 43 44 45 46 47 92 81 70 59 48 11 10 9 13 14 15 26 27 28 29 30 31 33 34 35 36 37 38 41 1 8 12 25 32 39 50 61 72 83 m y x eee 1 suggested solder pad layout top view 94 95 96 97 98 99 100 101 102 103 104 93 82 71 60 49 24 23 22 21 20 19 18 17 16 7 6 5 4 3 2 40 51 62 73 84 85 86 87 88 89 90 91 74 75 76 77 78 79 80 63 64 65 66 67 68 69 52 53 54 55 56 57 58 42 43 44 45 46 47 92 81 70 59 48 11 10 9 13 14 15 26 27 28 29 30 31 33 34 35 36 37 38 41 1 8 12 25 32 39 50 61 72 83 0.0000 1.2700 2.5400 0.3175 0.3175 4.4450 5.7150 6.9850 1.4675 5.7158 6.9421 4.4458 6.3500 6.3500 3.8100 3.8100 1.2700 0.3175 0.3175 0.0000 1.2700 3.1758 1.9058 0.6358 0.0000 0.6342 1.9042 3.1742 4.4442 5.7142 6.9865 2.7375 4.0075 5.2775 6.5475 6.9888 1.0900 2.3600 4.4950 5.7650 5.0800 5.0800 2.5400 2.5400 23 a b c d e f g h j l m n p r t k
prerelease ltm4600 22 4600p pin name pin name pin name pin name pin name pin name pin name pin name a1 - b1 v in c1 - d1 v in e1 - f1 v in g1 pgnd h1 - a2 - b2 - c2 - d2 - e2 - f2 - g2 - h2 - a3 v in b3 - c3 - d3 - e3 - f3 - g3 - h3 - a4 - b4 - c4 - d4 - e4 - f4 - g4 - h4 - a5 v in b5 - c5 - d5 - e5 - f5 - g5 - h5 - a6 - b6 - c6 - d6 - e6 - f6 - g6 - h6 - a7 v in b7 - c7 - d7 - e7 - f7 - g7 - h7 pgnd a8 - b8 - c8 - d8 - e8 - f8 - g8 - h8 - a9 v in b9 - c9 - d9 - e9 - f9 - g9 - h9 pgnd a10 - b10 - c10 v in d10 - e10 v in f10 - g10 - h10 - a11 v in b11 - c11 - d11 - e11 - f11 - g11 - h11 pgnd a12 - b12 - c12 v in d12 - e12 v in f12 - g12 - h12 - a13 v in b13 - c13 - d13 - e13 - f13 - g13 - h13 pgnd a14 - b14 - c14 v in d14 - e14 v in f14 - g14 - h14 - a15 fadj b15 - c15 - d15 - e15 - f15 - g15 - h15 pgnd a16 - b16 - c16 - d16 - e16 - f16 - g16 - h16 - a17 sv in b17 - c17 - d17 - e17 - f17 - g17 - h17 pgnd a18 - b18 - c18 - d18 - e18 - f18 - g18 - h18 - a19 extv cc b19 - c19 - d19 - e19 - f19 - g19 - h19 - a20 - b20 - c20 - d20 - e20 - f20 - g20 - h20 - a21 v oset b21 - c21 - d21 - e21 - f21 - g21 - h21 - a22 - b22 - c22 - d22 - e22 - f22 - g22 - h22 - a23 - b23 comp c23 - d23 sgnd e23 - f23 run/ss g23 fcb h23 - pin name pin name pin name pin name pin name pin name pin name pin name j1 pgnd k1 - l1 - m1 - n1 - p1 - r1 - t1 - j2 - k2 - l2 pgnd m2 pgnd n2 pgnd p2 v out r2 v out t2 v out j3 - k3 - l3 - m3 - n3 - p3 - r3 - t3 - j4 - k4 - l4 pgnd m4 pgnd n4 pgnd p4 v out r4 v out t4 v out j5 - k5 - l5 - m5 - n5 - p5 - r5 - t5 - j6 - k6 - l6 pgnd m6 pgnd n6 pgnd p6 v out r6 v out t6 v out j7 - k7 pgnd l7 - m7 - n7 - p7 - r7 - t7 - j8 - k8 l8 pgnd m8 pgnd n8 pgnd p8 v out r8 v out t8 v out j9 - k9 pgnd l9 - m9 - n9 - p9 - r9 - t9 - j10 - k10 l10 pgnd m10 pgnd n10 pgnd p10 v out r10 v out t10 v out j11 - k11 pgnd l11 - m11 - n11 - p11 - r11 - t11 - j12 - k12 - l12 pgnd m12 pgnd n12 pgnd p12 v out r12 v out t12 v out j13 - k13 pgnd l13 - m13 - n13 - p13 - r13 - t13 - j14 - k14 - l14 pgnd m14 pgnd n14 pgnd p14 v out r14 v out t14 v out j15 - k15 pgnd l15 - m15 - n15 - p15 - r15 - t15 - j16 - k16 - l16 pgnd m16 pgnd n16 pgnd p16 v out r16 v out t16 v out j17 - k17 pgnd l17 - m17 - n17 - p17 - r17 - t17 - j18 - k18 - l18 pgnd m18 pgnd n18 pgnd p18 v out r18 v out t18 v out j19 - k19 - l19 - m19 - n19 - p19 - r19 - t19 - j20 - k20 - l20 pgnd m20 pgnd n20 pgnd p20 v out r20 v out t20 v out j21 - k21 - l21 - m21 - n21 - p21 - r21 - t21 - j22 - k22 - l22 pgnd m22 pgnd n22 pgnd p22 v out r22 v out t22 v out j23 pgood k23 - l23 - m23 - n23 - p23 - r23 - t23 - package descriptio u pin assignment tables (arranged by pin number)
prerelease ltm4600 23 4600p information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. package descriptio u pin name g1 pgnd h7 h9 h11 h13 h15 h17 pgnd pgnd pgnd pgnd pgnd pgnd j1 pgnd k7 k9 k11 k13 k15 k17 pgnd pgnd pgnd pgnd pgnd pgnd l2 l4 l6 l8 l10 l12 l14 l16 l18 l20 l22 pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd m2 m4 m6 m8 m10 m12 m14 m16 m18 m20 m22 pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd n2 n4 n6 n8 n10 n12 n14 n16 n18 n20 n22 pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd pgnd pin name p2 p4 p6 p8 p10 p12 p14 p16 p18 p20 p22 v out v out v out v out v out v out v out v out v out v out v out r2 r4 r6 r8 r10 r12 r14 r16 r18 r20 r22 v out v out v out v out v out v out v out v out v out v out v out t2 t4 t6 t8 t10 t12 t14 t16 t18 t20 t22 v out v out v out v out v out v out v out v out v out v out v out pin name a3 a5 a7 a9 a11 a13 v in v in v in v in v in v in b1 v in c10 c12 c14 v in v in v in d1 v in e10 e12 e14 v in v in v in f1 v in pin name a15 fadj a17 sv in a19 extv cc a21 v oset b23 comp d23 sgnd f23 run/ss g23 fcb j23 pgood pin assignment tables (arranged by pin number)
prerelease pre-release ltm4600 24 4600p ? linear technology corporation 2005 lt 1105 ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com typical applicatio u 1 . 8v , 10a r egu l a t or 4600 f19 c1, c2: tdk c3216x5r1e106mt c3: taiyo yuden, jmk316bj226ml-t501 c4: sanyo pos cap, 4tpe470mcl 1.8v at 10a 4.5v at 20v r1 100k extv cc run comp fcb v out pgood fb sv in pgnd sgnd c1 10 f 25v c2 10 f 25v c5 100pf c4 470 f 4v pgood c3 22 f x3 v in ltm4600 f set r2 49.9k 1% this product contains technology licensed from silicon semiconductor corporation. ?

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